1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and more particularly, to a static-type semiconductor memory circuit comprising saturation-type memory cells and incorporating delay circuits therein.
2. Description of the Prior Art
In recent years, a variety of semiconductor memory circuits have been proposed. The present invention especially refers to the static-type semiconductor memory circuit comprising saturation-type semiconductor memory cells and incorporating delay circuits therein. The delay circuits are connected to word lines to improve both the rising and falling characteristics of the word lines and of the hold lines. The presence of such delay circuits makes it possible to achieve high speed transition of the word lines from a selection state to a non-selection state and vice versa. This results in a very short access time for the memory cells. Further, such time delay circuits provide an advantage in that the short access time is obtained without increasing the memory cell current, that is, without increasing the power consumption. However, there is a problem with the such delay circuits in that an undesired double selection of word lines tends to often occur.